(1) Field of the Invention
The present invention relates to the formation of integrated circuits on semiconductor substrates, and more particularly a method for forming a patterned planar conductive layer.
(2) Description of the Prior Art
Today's Ultra Large Scale Integration (ULSI) on the semiconductor substrate is in part due to advances in high resolution photolithographic techniques and to advances in plasma etching of the various conducting and insulating layers on the substrate. However, the accumulated effect of depositing and the etching of patterns in these layers, one patterned layer on top of the other, has resulted in irregular or substantially non-planar surface with micrometer and submicrometer feature sizes on a otherwise microscopically planar substrate.
These irregular surface features cause a number of process and reliability problems. For example, incomplete exposure of photoresist and thickness variations of the photoresist due to the leveling effect over recesses in the underlying patterned layer, result in incomplete development of the photoresist image. This results in unwanted photoresist residue which acts to mask the underlying layer during etching to define the patterned layer. This results in shorts when patterning conducting layers, such as polysilicon, or can lead to open contacts when etching via contacts in insulating layers. This problem is especially troublesome on ULSI circuits where the feature dimensions are submicrometer in size.
One particular area in ULSI semiconductor processing where this type of nonplanar structures occur is the formation of the electrical interconnecting patterns used to contact source/drains on Field Effect Transistors (FETs). For example, this is particularly the case for forming the bit line wiring used on dynamic random access memory (DRAM) and static random access memory (SRAM) chips. Generally this wiring makes contact to the source/drain of the FET and is patterned from a doped polysilicon or polysilicon/silicide layer that is formed over the FET gate electrode or the interconnecting patterned layer, that is also usually formed from polysilicon or polysilicon/silicide layer.
Because of the high density of memory cells on the chip, adjacent FET are closely spaced and their gate electrodes have horizontal dimensions that are submicrometer in width, for example about 0.5 micrometers or less. On the other hand the gate electrode, composed of the doped polysilicon layer and the insulating layer formed thereon, can be about 0.5 micrometers or more in height. The spaces between the gate electrodes are also submicrometer in width, for example about 0.5 micrometers or less in width, and have source/drain areas to which the bit lines must make electrical contact. Therefore, the bit line, composed of a patterned polysilicon or polysilicon/silicide layer, must pass over the patterned first polysilicon layer forming the gate electrode and interconnecting word line. Therefore, the bit lines wiring is required to traverse a surface having recesses or spaces that have aspect ratios that are quite large, for example equal to or greater than one.
This rough surface topography makes it difficult to define the photoresist pattern without image distortion. Furthermore, residue remaining after the photoresist image is formed over this rough topography can act as an etch stop when the underlying polysilicon layer is etched.
One approach of eliminating this problem is to form a planarized insulating layer over the patterned polysilicon layer that comprises the FET gate electrode and interconnecting word lines. The self-aligned source/drain contact openings are then etched in this planar insulating layer to provide the bit line electrical contact. Several methods have been used to planarize this layer, for example, a planarizing photoresist or spin-on-glass etch back can be used. Another approach is to use a low flow temperature glass, such as phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG) or by using a biased plasma enhanced CVD (PECVD), and similar techniques.
In order to preserve the high device density for ULSI applications, such as on DRAM and SRAM chips, the contacts openings to the FET source/drains must be self-aligned. That is, the contact openings are made in the insulating layer and are made overlapping the gate electrodes of the FETs. The silicon oxide or nitride sidewalls and the insulating layer over the gate electrode is then used as the defining layer for the source/drain contact. If the insulating is made planar, however, it is difficult to control the etching of the openings in the thick insulator without over etch. Even if silicon nitride is used as an etch stop over the electrode, the etch rate selectivity of the oxide to the nitride is at best about 2 to 1. This then results in electrical shorts between the patterned second polysilicon layer forming the bit line, and the polysilicon gate electrode.
A method for achieving a planar insulating layer and minimizing the overetch problem has been described by C. A. Bollinger et al, U.S. Pat. No. 5,200,358. In this patent, a doped insulator is deposited such as BPSG forming a conformal layer and filling the narrow spaces between the gate electrodes. The layer is then etched back to provide a local planarizing effect. The overlapping contact opening is then etched in the BPSG glass which etches faster than the silicon oxide or silicon nitride, improving the etch selectivity.
Although there are a number of methods available for forming a planar insulating layer and etching overlapping contact opening, there still remains the need to further improve the photoresist image quality and to form overlapping contacts that can avoid etching through a thick insulating layer.